Atomic layer deposition of interpoly oxides in a non-volatile memory device

ABSTRACT

Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a division of U.S. patent application Ser.No. 10/243,379, filed Sep. 12, 2002, incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to integrated circuits, and moreparticularly to nonvolatile integrated memories.

FIG. 1 shows a cross section of a stacked gate nonvolatile memory cellsuch as used in flash and non-flash electrically erasable programmableread only memories (EEPROM). Conductive floating gate 110, made of dopedpolysilicon, overlies monocrystalline silicon substrate 120. Silicondioxide 130 insulates the floating gate from the substrate. N typesource/drain regions 140 in substrate 120 are separated by P typechannel region 150. Channel region 150 is directly below the floatinggate. Dielectric 160 separates the floating gate from control gate 170made of doped polysilicon.

The memory cell is read by applying a voltage between the regions 140,applying a voltage between one of the regions 140 and control gate 170,and detecting a current through the other one of the regions 140. Thememory cell is written (programmed or erased) by modifying a charge onfloating gate 110. Floating gate 110 is completely insulated on allsides. To modify the charge on the floating gate, electrons aretransferred between the floating gate and substrate 150 through oxide130. The electrons can be transferred by Fowler-Nordheim tunneling orhot electron injection. See “Nonvolatile Semiconductor MemoryTechnology” (1998) edited by W. D. Brown and J. E. Brewer, pages 10-25,incorporated herein by reference. The electron transfer requires avoltage to be established between the floating gate and a substrateregion (the substrate region can be channel 150 or a source/drain region140). This voltage is established by creating a voltage between thesubstrate region and the control gate. The control gate voltage iscoupled to the floating gate. To reduce the voltage required to becreated between the substrate region and the control gate, a highcapacitive coupling is needed between the floating and control gates. Ahigh specific capacitance (capacitance per unit area) can be obtainedbetween the floating and control gates by reducing the thickness ofdielectric layer 160. However, dielectric layer 160 functions as abarrier to a charge leakage from the floating gate to the control gate.Therefore, dielectric 160 has to be a high quality, thin, uniformdielectric in order to provide good data retention (low leakage) andensure a predictable high capacitive coupling between the floating andcontrol gates.

Dielectric 160 can be silicon dioxide as shown in FIG. 1. However, asthe dimensions of the devices continues to shrink, the thickness of theSiO₂ layer must also decrease to maintain the same capacitance betweenthe floating gate and the control gate. Thicknesses of less than 2 nmare expected in the future. However, the occurrence of high tunnelingcurrent through such thin layers of SiO₂ requires that alternativematerials be considered. ONO (silicon dioxide, silicon nitride, silicondioxide) has been used as dielectric layer 160. See U.S. Pat. No.4,613,956 issued Sep. 23, 1986 to Peterson et al. The nitride layer hasa higher dielectric constant than silicon dioxide, thus increasing thecapacitive coupling between the floating gate and the control gate. Thehigher capacitive coupling allows a thicker layer to be used to reduceleakage current without diminishing the capacitive coupling. Anotheroption is a combination of silicon dioxide and oxynitride layers fordielectric layer 160. Thus, according to U.S. Pat. No. 6,274,902, asilicon dioxide layer is thermally grown on floating gate polysilicon,and an oxynitride layer is deposited by LPCVD (low pressure chemicalvapor deposition) on the silicon dioxide.

SUMMARY

This section summarizes some features of the invention. The invention isdefined by the appended claims that are incorporated into this sectionby reference.

In some embodiments of the present invention, the silicon nitride layerof the ONO is substituted with a high-k dielectric layer formed by adeposition technique known as atomic layer deposition (ALD).(“High-k”refers to materials having a dielectric constant greater than about 4).Using ALD, single monolayers of the high-k material can be formed at atime, resulting in a nearly perfect crystal structure with fewer crystaldefects or pin holes. Reducing the number of defects reduces the numberof defect states, which allow undesired electron transport across theoxide barrier. Therefore the leakage current is minimized, while thedielectric constant remains higher than that of silicon dioxide by afactor of 2-6 times. Aspects of the invention include the method forforming the atomic monolayers, and their inclusion in an interpoly stackof a flash memory cell.

In a first embodiment of the invention, the middle layer of siliconnitride in a conventional ONO interpoly stack is substituted with ahigh-k dielectric film deposited using an ALD process. After the ALDprocess, a second layer of silicon dioxide can be deposited on thesurface of the high-k layer, using the usual high temperature oxide(HTO) techniques.

Optionally, other dielectric layers (e.g. silicon nitride, oxynitride)can be formed on the thermally grown silicon dioxide layer.

In some embodiments, dielectric 160 can include only layers made withALD, rather than a mutli-layer stack of HTO/high-k oxide/HTO.

The invention is applicable to split gate memories and other flash andnon-flash floating gate memories, known or to be invented. Otherfeatures of the invention are described below. The invention is definedby the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross section of a prior art nonvolatile memory cell.

FIGS. 2-4 show cross sections of nonvolatile memory cells during aprocess of fabrication according to some embodiments of the presentinvention.

DETAILED DESCRIPTION

FIG. 2 illustrates a cross section of a nonvolatile memory cell at anintermediate stage of fabrication. In the illustrative embodiment beingdescribed, substrate 120 is a suitably doped (e.g. P-doped)monocrystalline silicon substrate; appropriate wells (not shown) havebeen formed in the substrate, as described in U.S. Pat. No. 6,355,524entitled “Nonvolatile Memory Structures and Fabrication Methods”, filedAug. 15, 2000 by H. T. Tuan et al., incorporated herein by reference.Other types of substrates, including non-silicon substrates, can also beused. The invention is not limited by any particular wells or dopingtypes.

Source/drain regions 140 are formed by doping. Additional layers (notshown) may be formed to provide select gates, erase gates, or otherfeatures. See the aforementioned U.S. Pat. No. 6,355,524 B1 for anexemplary memory fabrication process that can be modified to incorporatethe atomic-layer deposition oxide described above.

Semiconductor substrate 120 (monocrystalline silicon or some othermaterial) is processed to form a suitably doped channel region 150 (typeP in FIG. 2, but an N type channel can also be used). Dielectric 130 isformed on substrate 120 over channel 150. Dielectric 130 may bethermally grown silicon dioxide or some other type of dielectric, and isknown as “tunnel oxide” because the memory cell can be erased by theFowler-Nordheim tunneling of electrons from the floating gate tosubstrate 120. In some embodiments, the oxide is grown at around 800C-900 C, by dry oxidation to a thickness of 8-10 nm. The invention isnot limited to Fowler-Nordheim tunneling or silicon dioxide.

Then polysilicon layer 110 is deposited on top of the tunnel oxide anddoped during or after deposition. The polysilicon layer can befabricated using, for example, a POLYGEN chamber manufactured by AppliedMaterials, Inc. of Santa Clara, Calif. The polysilicon layer may be 1200A-1800 A thick, deposited by low pressure chemical vapor deposition(LPCVD), and doped with phosphorus to a concentration of 1E19-1E20atoms/cm³. The dopant may be applied via a gas mixture comprisingSiH₄/PH₃ at 610 C, at 250-300 Torr, or by ion implantation.

Polysilicon layer 110 will provide the floating gates and, possibly,other circuit elements as needed for the peripheral circuitry. Suchelements may include interconnects, transistor gates, resistors andcapacitor plates.

In a first embodiment, shown in FIG. 2, a trilayer interpoly dielectriclayer is formed upon the polysilicon layer 110. The trilayer interpolydielectric 200 may be preferably a three layer structure, as denoted byreference numerals 310, 410, and 420 in FIG. 2. For example, layers 310,410, and 420 may be silicon oxide, a high-k dielectric material, andsilicon oxide respectively. Layer 200 may have a total thickness fromabout 13 nm to 160 nm. This structure is often called the interpolydielectric since it is sandwiched between the phosphorous dopedpolysilicon layer 110 constituting the floating gate for a flash memorycell, and a second polysilicon layer 170 that forms the control gate forthe cell. The first and third layers 310 and 420 of the interpolydielectric are the silicon dioxide layers which may be formed as a HighTemperature Oxide (HTO). The middle layers 410 of the interpolydielectric are the high-k materials formed by sequential ALD of singlemonolayers of one or more high-k materials, for example, aluminum oxide,to form a continuous high-k film.

A number of high-k materials are of interest in forming the dielectriclayers (e.g. layer 410) for thin capacitors. Table I below compares somedielectric materials with high-k materials which can be formed usingatomic layer deposition. TABLE I Material Dielectric Constant Energy Gap(eV) SiO₂ 3.9 9.0 Si₃N₄ 7.0 5.0 Al₂O₃ 8.0 7.0 HfO₂ 20-25 5.7 ZrO₂ 20-255.2 TaO₂ 60-80 3.2 TiO₂ 23-26 4.2

According to Table I, aluminum oxide is among the most desirablematerials because of its combination of a high energy gap for lowleakage current, and a high dielectric constant for high capacitivecoupling. The dielectric layer 410 formed by the ALD method of thepresent embodiment has a high dielectric constant, a low defect density,and fewer interface traps than for example CVD films, and so thereliability of the interpoly dielectric layer can be increased in flashmemory cells. It is consequently possible to prevent charge leakage fromthe floating gate to the control gate and facilitate Fowler-Nordheimtunneling, thereby enhancing the erase operation. The increased couplingratio leads to reduced applied voltage requirements, which, in turn,leads to longer life of the flash memory cells made in accordance withthis invention.

Because of the desirable properties of aluminum oxide, the remainder ofthis specification will deal primarily with this material as the high-kdielectric material to be deposited by ALD. However it is clear that thetechniques disclosed herein may be applied to other high-k dielectricmaterials (e.g. those listed in Table I) that can be deposited usingALD.

In the first embodiment of FIG. 2, a first layer of silicon oxide 310(FIG. 2) is formed as a high temperature oxide in a low pressurechemical vapor deposition (LPCVD) process on the top surface ofpolysilicon layer 110. The silicon oxide may be used to minimize orprevent subsequent processing, such as the deposition of the aluminumoxide, from deleteriously effecting the first polysilicon layer. Inparticular, the silicon oxide layer has a thickness suitable to minimizeor prevent oxidation of the first polysilicon layer during formation ofthe aluminum oxide high-k layers. In this embodiment, the silicon oxidelayer 310 may have a thickness of about 5 nm, or in the range of 3 to 8nm. The silicon oxide layer 310 can be obtained at 750° C. by reactingdichlorosilane SiH₂Cl₂ in an N₂O atmosphere at 300-500 mTorr. Otherthicknesses, processes, and process parameters may also be used.

The second layer of the trilayer structure of the interpoly dielectric200 is the high-k film formed by ALD. The ALD process is outlined by theflow chart in FIG. 3. The ALD process may include, as a preliminarystep, the preparation of the wafer surface by cleaning. In oneembodiment, the cleaning solution may be a mixture of NH₄OH, H₂O₂ anddeionized water, that is warmed to 45-55 C. The cleaning solution isfollowed by a hydrofluoric rinse, and then followed by another mixedchemical cleaning in a solution of HCl, H₂O₂ and deionized water. Thewafer is left with a hydroxy-terminated surface structure Si—O—H on thetop of layer 310.

The high-k, e.g. aluminum oxide, layer 410 is next formed over thecleaned HTO surface by introducing an aluminum tri-methyl precursor gasalternating with water vapor, into the reaction chamber. Genus, Inc. ofSunnyvale, Calif. manufactures an ALD tool that can be used inconnection with the process described herein. Although the processdescribed herein is well suited to solving the problem of depositingAl₂O₃ on hydroxy-terminated silicon surfaces, it is entirely possible touse this process to deposit aluminum oxide on other surfaces includingsilicon dioxide, silicon oxynitride, silicon germanium, and onsilicates.

As described in the flow chart of FIG. 3, for a first embodiment of theinvention, a first step 30, is to introduce a Al(CH₃)₃ precursor gasinto a Genus LYNX Series Model ALD Chamber containing a pre-cleanedsubstrate at a temperature of 200-400 C. The Al(CH₃)₃ precursor gas isat a pressure of 10-100 Torr, and chemisorbs onto the surface of thesilicon oxide layer 310 until the surface is saturated with Al atoms. Asa second step 40, the chamber is then purged with an inert gas such asnitrogen, helium, or argon to remove any excess or residual aluminumtri-methyl or undesirable reactants. Next, in a third step 50, anoxidizing gas is introduced, such as water vapor or ozone. The watervapor oxidizes the Al chemisorbed onto the substrate surface, until thesurface is saturated with a monolayer of aluminum oxide. Saturation ofthe surface typically occurs within milliseconds of exposure to theactivating gases. Lastly, in a fourth step 60, the chamber is purgedwith an inert gas, such as argon or nitrogen, to reduce or eliminate theoxidizing gas and any undesired reactants. By repeating the steps 30through 60, a high-k thin film can be deposited, a single monolayer at atime.

The ALD process is inherently growth rate limited by the number ofcycles of alternate exposure to the aluminum tri-methyl compound, andthe oxidizing gas, with appropriate purging. For this embodiment thetotal thickness of the high-k dielectric layer 410 is about 8 nm, or inthe range of 5 to 13 nm. The high-k film in this example is amorphousaluminum oxide, with a better atom-to-atom arrangement than may beobtained with other deposition methods, for example, chemical vapordeposition (CVD). The film is stoichiometric, i.e. Al₂O₃ rather thanAl₂-xO₃, and should have no dangling bonds at the interface surface.

A second silicon oxide layer 420 may be formed on top of the high-kdielectric layer 410, as, for instance, a high temperature oxide by theLPCVD method. As described previously, such an oxide deposition can beperformed at 750° C. by reacting dichlorosilane SiH₂Cl₂ in an N₂Oatmosphere at 300-500 mTorr. An exemplary thickness of layer 420 is 4nm. Other thicknesses, processes, and process parameters may also beused.

Therefore, in one embodiment the overall thickness of dielectric layer410, including silicon oxide layer 310, a high-k ALD aluminum oxidelayer 410, and a silicon oxide layer 420 in a stack is 5+8+4 nm=17 nm inone embodiment.

Other high-k materials can be fabricated using the ALD process describedabove, and substituted as layer 410 for the aluminum oxide in the aboveexample. For example other embodiments are shown in Table II below,which use mostly tetra-chloride precursors and water vapor to form themonolayers of the respective oxides. Continuous monolayer films may beformed by sequential introduction of the following precursor gases,followed by water vapor, under the following conditions, in the reactormentioned above. TABLE II High-k material Precursor Chamber TemperatureChamber Pressure Al₂O₃ Al(CH₃)₃, H₂O 200-400 C. 10-100 Torr HfO₂ HfCl₄,H₂O 200-350 C. 10-100 Torr ZrO₂ ZrCl₄, H₂O 200-350 C. 10-100 Torr TaO₂TaCl₅, H₂O 250-300 C. 10-100 Torr TiO₂ TiCl₄, H₂O 200-400 C. 10-100 Torr

An annealing process can be included after deposition of the high-kmaterial, if it is found that the film has less leakage or a higherbreakdown voltage with such an extra anneal. For example, a RapidThermal Anneal (RTA) process may be performed after the deposition toanneal the high-k film. The process parameters for the RTA process mayinclude a temperature of 950-960 C, and a pressure of 1 to 500 Torr ofAr for 30 seconds.

Known techniques can be used to complete the memory fabrication. Dopedpolysilicon 170, or some other conductive material, is deposited toprovide the control gates and possibly wordlines, each of which providesthe control gates for a row of memory cells. The stack of layers 170,420, 410, 310, 110, 130 are patterned as needed, using an etch process.

For instance, the stack of layers including the high-k dielectric layercan be patterned by applying a photoresist mask to thepolysilicon/interpoly dielectric stack. Such a mask protects the areasunderneath the mask and exposes the unwanted areas to an etchant. ACl₂/HBr chemistry plasma etch will etch the top polysilicon layer. Theunderlying high-k layers may be etched using 6 mTorr chamber pressureand 500 top source power/−100 V back bias voltage. The etchant gasesinclude chlorine Cl₂, flowing at 50 SCCM (standard cubic centimeters perminute), and argon Ar, flowing at 100 SCCM at a pressure of 8 Torrback-side pressure. Lastly, the bottom polysilicon layer is etched usinga Cl₂/HBr chemistry plasma etch. The aluminum oxide and top and bottompolysilicon are etched through the mask openings to form stripsextending in the bitline direction through the memory array.

In another embodiment, the top surface of oxide 420 may be nitrided, asshown in FIG. 4, to further improve the data retention. The capacitanceis also increased as nitrogen binds with silicon to form siliconnitride. The nitridation can be performed, for example, by ionimplantation, Remote Plasma Nitridation (RPN) or Decoupled PlasmaNitridation (DPN), using the processes described in U.S. Pat. No.6,074,954 issued on Jun. 13, 2000 to Lill et al. and incorporated hereinby reference. A thermal anneal can be performed at the end of thenitridation as described above for layer 110.

In some embodiments, the surface concentration of nitrogen atoms isabout 1E20 atom/cm³, and the thickness of the nitrided layer 420.1 atthe top of layer 420 is below 1 nm, as shown in FIG. 4.

In an alternative embodiment, the silicon oxide layers 310 and 420 ofFIG. 2 are omitted in favor of a continuous film of high-k ALDmonolayers between the floating gate polysilicon layer 110 and thecontrol gate polysilicon layer 170 of FIG. 2. In FIG. 5, such acontinuous high-k film 180 is formed directly on polysilicon layer 110using atomic layer deposition. The high-k layer may be aluminum oxide,as described above, by repeating the steps 30 through 60, to achieve atotal (physical) film thickness of approximately 10-20 nm. The finalfilm thickness may be adjusted in order to meet the original ONOelectrical performance requirements. However it is noted that anelectrical equivalent oxide thickness can be obtained with a dielectriclayer which is twice the thickness of the silicon dioxide film itreplaces, because of the increase in the dielectric constant. Therefore,the leakage current in such an embodiment may be expected to be farreduced, compared to the prior art oxide films. Of course, the otherhigh-k dielectric films listed in Table II also may be deposited by ALDand used in place of the aluminum oxide.

In some embodiments, the use of high-k atomic layer deposited interpolyfilms may not lead to a significant change in the total physicalthickness of dielectric 160. However, the specific capacitance betweenthe floating and control gates increases by a factor of two in someembodiments depending on the deposition conditions. Other capacitanceparameters can also be obtained. The increased capacitance can enhancethe write/erase performance of the memory cell at a given voltageapplied to the control gate, resulting in improved lifetime andreliability of the memory device.

Conductive layer 170 (FIG. 2), for example, doped polysilicon, is formedon the ALD-deposited surface of aluminum oxide layer 180 as describedabove in connection with FIG. 2. This layer will provide the controlgate. The structure is patterned and the fabrication is completed asdescribed above in connection with FIG. 2.

The films 170, 420, 410, 310, and 110 in FIG. 2 may be annealed duringthe activation of the polysilicon doping, or optionally, an additionalanneal process can be inserted here (after ALD step), if it is foundthat the device has a higher breakdown voltage or less leakage currentwith the inclusion of such an anneal. The process is the same as wasdescribed for the rapid thermal anneal of the two high temperature oxidelayers 310 and 420 of the ONO stack as shown in FIG. 2. The processparameters for the RTA are 950-960 C at a pressure of 1 to 500 Torr ofAr for 30 seconds.

The memory cells of FIGS. 2, 4, and 5 can be operated like the memorycell of FIG. 1. The memory can be programmed by Fowler-Nordheimtunneling of electrons from channel 150 or source/drain region 140 tofloating gate 110. The memory can be erased by Fowler-Nordheim tunnelingof electrons from the floating gate to channel 150 or a source/drainregion 140. In other embodiments, the memory is programmed by hotelectron injection, and erased by Fowler-Nordheim tunneling. In stillother embodiments, the memory is erased by tunneling of electrons fromthe floating gate to a separate erase gate (not shown). Other memorystructures, including split gate structures with select gates, and otherprogramming and erase mechanisms, known or to be invented, can also beused.

The invention is not limited to the embodiments described above. Forinstance, the invention is not limited to the particular atomic layerdeposition techniques or process parameters, layer thicknesses, or otherdetails. Likewise, the invention is not limited to the particular shapeof the floating and control gates or their positioning relative to eachother, and the invention is not limited to particular materials. Forexample, polysilicon 110 can be replaced with amorphous silicon,monocrystalline silicon, or their combinations. Silicon dioxide (SiO₂)can be replaced, or mixed with, silicon monoxide (we use the term“silicon oxide” to refer both to silicon dioxide and silicon monoxide).Other embodiments and variations within the scope of the invention, asdefined by the appended claims, will occur to practitioners in view ofthe disclosure herein.

1. A method for manufacturing an integrated circuit comprising anonvolatile memory, the method comprising: forming a first layer, thefirst layer being to provide one or more floating gates for thenonvolatile memory; forming a dielectric layer over the first layer,wherein forming the dielectric layer comprises forming a high-kdielectric layer by atomic layer deposition; forming a conductive layerseparated from the first layer by the dielectric layer, the conductivelayer providing one or more control gates for the nonvolatile memory;wherein the high-k dielectric layer comprises aluminum oxide; whereinforming the dielectric layer further comprises: forming a first siliconoxide layer over the first layer; forming the high-k dielectric layer onthe first silicon oxide layer; and forming a second silicon oxide layerover the high-k dielectric layer.
 2. The method of claim 1, furthercomprising patterning the first layer, the dielectric layer, and theconductive layer by lithographic processes after forming said conductivelayer.
 3. The method of claim 1, wherein the high-k dielectric layer hasa dielectric constant greater than 7.5.
 4. The method of claim 1,wherein the high-k dielectric layer comprises a high-k oxide layer. 5.The method of claim 1, further comprising nitriding the second siliconoxide layer.
 6. The method of claim 1 wherein forming the high-kdielectric layer over the first layer comprises: providing a cleansubstrate upon which the first layer has been formed, within a reactionchamber; introducing a metallic precursor gas into the chamber; purgingthe chamber with an inert gas; and introducing an oxidizing gas into thechamber whereby a monolayer of high-k oxide is deposited on thesubstrate.
 7. The method of claim 6, wherein the metallic precursor gasis Al(CH3)3.
 8. The method of claim 6, wherein the oxidizing gas iswater vapor or ozone.
 9. The method of claim 6, wherein forming thehigh-k dielectric layer comprises repeating the steps of: introducing ametallic precursor gas into the chamber; purging the chamber with aninert gas; introducing an oxidizing gas into the chamber; and purgingthe chamber with an inert gas, to make additional monolayers of thehigh-k dielectric layer.
 10. The method of claim 1 further comprising:(1) after forming the first silicon oxide layer and before forming thehigh-k dielectric layer, processing the first silicon oxide layer toform a hydroxy-terminated surface structure Si—O—H on a top surface ofthe first silicon oxide layer.
 11. The method of claim 10 wherein theoperation (1) comprises processing the first silicon oxide layer withH₂O₂ and/or NH₄OH.
 12. A method for manufacturing an integrated circuitcomprising a nonvolatile memory, the method comprising: forming a firstlayer comprising silicon, the first layer being to provide one or morefloating gates for the nonvolatile memory; forming a dielectric layerover the first layer, wherein forming the dielectric layer comprisesdepositing a first high temperature oxide over the first layer;depositing a high-k dielectric layer over the first oxide using atomiclayer deposition; depositing a second high temperature oxide over thehigh-k dielectric layer; and forming a conductive layer separated fromthe first layer by the dielectric layer, the conductive layer providingone or more control gates for the nonvolatile memory; wherein the high-kdielectric layer comprises aluminum oxide.
 13. The method of claim 12,wherein the high-k dielectric layer has a dielectric constant greaterthan 7.5.
 14. The method of claim 12, wherein the high-k dielectriclayer comprises a high-k oxide layer.
 15. The method of claim 12 whereindepositing the high-k dielectric layer over the first oxide comprisesdepositing a plurality of monolayers of aluminum oxide by atomic layerdeposition over the first layer.
 16. A method for manufacturing anintegrated circuit comprising a nonvolatile memory, the methodcomprising: (1) forming a first layer, the first layer being to provideone or more floating gates for the nonvolatile memory; (2) forming adielectric layer over the first layer, wherein forming the dielectriclayer comprises: (2A) forming a first silicon oxide layer over the firstlayer; (2B) processing the first silicon oxide layer to form ahydroxy-terminated surface structure Si—O—H on a top surface of thefirst silicon oxide layer; (2C) after forming the hydroxy-terminatedsurface structure, forming a high-k dielectric layer on the firstsilicon oxide layer; (3) wherein the method further comprises forming aconductive layer separated from the first layer by the dielectric layer,the conductive layer providing one or more control gates for thenonvolatile memory.
 17. The method of claim 16 wherein the operation(2B) comprises: (2B-1) processing the first silicon oxide layer with asolution of a mixture of NH₄OH, H₂O₂ and deionized water.
 18. The methodof claim 17 wherein the solution is at 45-55° C.
 19. The method of claim17 wherein the operation (2B) further comprises: (2B-2) processing thefirst silicon oxide layer with a solution of HCl, H₂O₂ and deionizedwater.
 20. The method of claim 19 wherein the operation (2B-2) isperformed after (2B-1).
 21. The method of claim 20 wherein the operation(2B) further comprises, between the operations (2B-1) and (2B-2),processing the first silicon oxide layer with a hydrofluoric rinse. 22.The method of claim 16 wherein the operation (2B) comprises processingthe first silicon oxide layer with a solution of HCl, H₂O₂ and deionizedwater.
 23. The method of claim 16 wherein the high-k dielectric layercomprises aluminum oxide.
 24. The method of claim 16 wherein the high-kdielectric layer is formed using a chlorine containing precursor. 25.The method of claim 24 wherein the high-k dielectric layer comprises oneor more of HfO₂, ZrO₂, TaO₂, TiO₂.
 26. A method for manufacturing anintegrated circuit comprising a nonvolatile memory, the methodcomprising: (1) forming a first layer, the first layer being to provideone or more floating gates for the nonvolatile memory; (2) forming adielectric layer over the first layer, wherein forming the dielectriclayer comprises: (2A) forming a first silicon oxide layer over the firstlayer; (2B) processing the first silicon oxide layer with H₂O₂ and/orNH₄OH; (2C) after the operation (2B), forming a high-k dielectric layeron the first silicon oxide layer; (3) wherein the method furthercomprises forming a conductive layer separated from the first layer bythe dielectric layer, the conductive layer providing one or more controlgates for the nonvolatile memory.
 27. The method of claim 26 wherein theoperation (2B) comprises: (2B-1) processing the first silicon oxidelayer with a solution of a mixture of NH₄OH, H₂O₂ and deionized water.28. The method of claim 27 wherein the solution is at 45-55° C.
 29. Themethod of claim 27 wherein the operation (2B) further comprises: (2B-2)processing the first silicon oxide layer with a solution of HCl, H₂O₂and deionized water.
 30. The method of claim 29 wherein the operation(2B-2) is performed after (2B-1).
 31. The method of claim 30 wherein theoperation (2B) further comprises, between the operations (2B-1) and(2B-2), processing the first silicon oxide layer with a hydrofluoricrinse.
 32. The method of claim 26 wherein the operation (2B) comprisesprocessing the first silicon oxide layer with a solution of HCl, H₂O₂and deionized water.
 33. The method of claim 26 wherein the high-kdielectric layer comprises aluminum oxide.
 34. The method of claim 26wherein the high-k dielectric layer is formed using a chlorinecontaining precursor.
 35. A method for manufacturing an integratedcircuit comprising a nonvolatile memory, the method comprising: (1)forming a first layer, the first layer being to provide one or morefloating gates for the nonvolatile memory; (2) forming a dielectriclayer over the first layer, wherein forming the dielectric layercomprises: (2A) forming a silicon oxide layer over the first layer; and(2B) forming a high-k dielectric layer on the first silicon oxide layer;(3) wherein the method further comprises forming a conductive layerseparated from the first layer by the dielectric layer, the conductivelayer providing one or more control gates for the nonvolatile memory;wherein forming the high-k dielectric layer is formed using aclorine-containing precursor.